In digital integrated circuits which must produce a wide variety of signal patterns, it is often necessary to design special counters and/or state machines to produce the desired results. An example of this application is in the field of digital imaging, where a charge coupled device (CCD) imager is employed in much the same manner as traditional silver-halide film. A CCD imager is a digital device which usually requires a substantial number of input signals with specific and unique characteristics. These signals are often referred to as "clocks", since they are usually periodic in nature. However, due to the operating tolerances of the various electronic devices employed in digital imaging systems, it is often desirable or necessary to be able to slightly alter the duty cycle and/or phase of these CCD clocks. Specifically, it is desirable to be able to alter pulse width and pulse location within each pixel period. Traditionally, this as been accomplished with analog delay circuits, synchronous digital techniques and/or ad hoc approaches. The disadvantages of these approaches are significant. The analog delay circuits are expensive and often inaccurate. Most of the digital techniques require high frequency crystal oscillators which, in addition to being more expensive, can also result in undesirable levels of radiated electromagnetic interference. Rapid prototyping of these higher speed circuits with programmable logic is often impossible, thus forcing engineers to commit their designs to more expensive ASIC (Application Specific Integrated Circuit) technology before they have had the opportunity to test them in the system environment. Most of these techniques do not allow for in-system adjustment or tuning for optimal performance. This invention presents a method which overcomes these difficulties while also providing increased flexibility.